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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES 16 Bits Resolution with No Missing 16-Bit Codes Throughput: 550 kSPS (Warp mode) 450 kSPS (Normal mode) 380 kSPS (Impulse mode) INL: 3LSB Max ( 0.0046 % of Full-Scale) S/(N+D): 89 dB Typ @ 10 kHz THD: -95 dB Typ @ 10 kHz Pseudo-Differential Analog input range: 0V to VREF with VREF up to VDD No Pipeline Delay Single Supply Operation 5V and 2.7V with 2.5V/3V/5V logic interface Multiple ADCs Daisy Chain and Busy Indicator Serial Interface SPI/QSPI/ Wire/DSP compatible 30 mW @ 5V/380ksps, TBD @ 3V Typical Power Dissipation, 80 W @ 1 kSPS Stand-by current ( acquisition phase ): 1 A Max -SOIC Package ( -SO8 size ) Pin-to-Pin Compatible with the AD7685, AD7687, AD7688 Battery Powered Equipment Data Acquisition Instrumentation Medical Instruments Process Control GENERAL DESCRIPTION
550kSPS 16-BIT ADC in SO AD7686*
FUNCTIONAL BLOCK DIAGRAM
VDD REF
AD7686
IN+
OVDD
SDI
IN-
SWITCHED CAP DAC
CONTROL LOGIC
SCK
SDO
CNV
GND
CLOCK
SO/SOT23 16 Bit ADC
Type / kSPS 100 kSPS True Differential Pseudo Differential Unipolar AD7680
250 kSPS AD7687 AD7684 AD7685 AD7683
380 - 550 kSPS AD7688 AD7686
The serial interface features the possibility to "Daisy chain" several ADCs on a single 3 wires bus and provides an optionnal Busy indicator. The AD7686 is hardware factory calibrated. It is fabricated using CMOS process and is housed in 10-lead SOIC package with operation specified from -40C to +85C.
PRODUCT HIGHLIGHTS
The AD7686 is a 16-bit, 550 kSPS, charge redistribution successive-approximation, Analog-to-Digital Converter which operates from a single power supply. It contains a high-speed 16-Bit sampling ADC without any missing code, an internal conversion clock, error correction circuits, and a flexible serial interface port. The part also contain a low noise, wide bandwidth, very short aperture delay track/hold circuit which can sample an analog input range from 0V to REF. The reference voltage REF is applied externally and can be set up to the supply voltage. It features a very high sampling rate mode asynchronous conversion rate applications, (Normal) and, for low power applications, power mode (Impulse) where the power is throughput. (Warp) and, for a fast mode a reduced scaled with the
1. Superior INL The AD7686 has a maximum integral non linearity of 3 LSB with no missing 16-bit code. 2. Fast Throughput. The AD7686 is a very high speed ( 550 kSPS in Warp mode and 450 kSPS in Normal mode), charge redistribution, 16-Bit SAR ADC with no pipeline delay. 3. 2.7V or 5V Single Supply Operation The AD7686 operates from a single supply, dissipates only TBD mW typical (Impulse), and even lower when a reduced throughput is used. It consumes 1 A maximum during the acquisition phase. 4. Serial Interface with OVDD, Daisy Chain and Busy 2.5V, 3 V or 5 V logic 3-wire serial interface arrangement compatible with SPI and DSP host.
*Patent pending. REV. PrD
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2003
PRELIMINARY TECHNICAL DATA
AD7686-SPECIFICATIONS
Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Analog Input CMRR Leakage Current at 25 Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate Complete Cycle Throughput Rate Complete Cycle Throughput Rate DC ACCURACY No Missing Codes Integral Linearity Error Transition Noise Gain Error2, TMIN to TMAX Gain Error Temperature Drift Offset Error2, TMIN to TMAX Offset Temperature Drift Power Supply Sensitivity AC ACCURACY Signal-to-Noise Spurious Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise+Distortion) Intermodulation Distortion Second Order Terms Third Order Terms -3 dB Input Bandwidth SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response REFERENCE External Reference Voltage Range External Reference Current Drain DIGITAL INPUTS Logic Levels V IL VIH IIL I IH DIGITAL OUTPUTS Data Format Pipeline Delay VOL VOH C
(TA = -40 C to +85 C, VREF = 5V, VDD = 5 V, OVDD = 2.3V to 5.25V, unless otherwise noted.)
Min 16 Typ Max Unit Bits V REF VDD + 0.1 TBD TBD TBD See Analog Input Section 1.8 550 2.2 450 2.6 380 V V V dB nA
Conditions
IN+ - ININ+ INfIN = TBD kHz 550kSPS Throughput
0 -0.1 -0.1
In In In In In In
Warp Mode Warp Mode Normal Mode Normal Mode Impulse Mode Impulse Mode
1 0 0 16 -3 0.7
s kSPS s kSPS s kSPS Bits LSB1 LSB % of FSR ppm/C LSB ppm/C LSB dB3 dB dB dB dB dB dB MHz ns ps rms ns V A
+3 TBD TBD TBD TBD TBD TBD
REF = 5 V
VDD = 5 V 5% fIN = TBD kHz fIN = TBD kHz fIN = TBD kHz fIN = TBD kHz fIN = TBD kHz,-60 dB Input 88 88
89 95 -95 89 29 TBD TBD TBD 2 5
TBD
Full-Scale Step TBD 550kSPS Throughput TBD
400 VDD
OVDD = 2.7V to 5.25V OVDD = 2.3V to 5.25V
-0.3 +2.0 +1.7 -1 -1
+0.8 OVDD + 0.3 OVDD + 0.3 +1 +1
V V V A A
ISINK = 500 A ISOURCE = -500 A
Serial 16-Bits Straight Binary Conversion Results Available Immediately After Completed Conversion 0.4 OVDD - 0.3
V V
NOTES 1 LSB means Least Significant Bit. With the 5 V input range, one LSB is 76.3 V. 2 See Definition of Specifications section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. 3 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA AD7686
Parameter POWER SUPPLIES VDD VDD Range OVDD Operating Current VDD OVDD Power Dissipation (VDD = 5V) Conditions Specified Performance 550 kSPS Throughput 4 VDD = 5V 380 kSPS Throughput 5 1 kSPS Throughput 5 During acquisition phase5 550 kSPS Throughput 4 TMIN to TMAX -40 Min 4.75 2.7 2.7 Typ 5 Max 5.25 5.25 5.25 Unit V V V mA A mW W W mW C
TBD TBD 30 80 TBD
TBD TBD TBD +85
TEMPERATURE RANGE 6 Specified Performance
NOTES 4 In Warp mode. 5 In Impulse mode. With all digital inputs forced to OVDD or GND respectively. 6 Contact factory for extended temperature range. Specifications subject to change without notice.
TIMING SPECIFICATIONS (-40 C to +85 C, VDD = 4.75 V to 5.25V, OVDD = 2.7 V to 5.25 V, unless otherwise stated)
O O
Symbol Refer to Figure 3 Conversion Time: CNV Rising Edge to Data available (Warp mode/ Normal mode/ Impulse mode) Acquisition Time Time Between Conversions CNV Pulse width SCK Period SCK Low Time SCK High Time SCK Falling Edge to Data remains Valid SCK Falling Edge to Data Valid delay CNV Low or SDI Low to SDO Valid (D15 MSB) CNV High or SDI High or 16th SCK Falling Edge to SDO High Impedance SDI valid Setup Time SDI valid Hold Time t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 11 t 12 t 13
Min
Typ
Max 1.4/1.8/2.2
Unit s ns s ns ns ns ns ns ns ns ns ns ns
0.7/0.9/1.1 400 1.8/2.2/2.6 5 20 8 8 5
Note 1
15 15 15 8 0
NOTES 1 In Warp mode, the maximum time between conversion is 1ms; otherwise, there is no required maximum time. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA
AD7686-SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS1 Analog Inputs IN+2, IN-, REF, . . . . . . GND -0.3 V to VDD + 0.3 Supply Voltages VDD, OVDD to GND . . . . . . . . . . . . . . . . -0.3 V to 7 VDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Digital Inputs to GND . . . . . . -0.3 V to OVDD + 0.3 Digital Outputs to GND . . . . -0.3 V to OVDD + 0.3 V V V V V Internal Power Dissipation 3 . . . . . . . . . . . . . . . . 325 mW Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150C Storage Temperature Range . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 See Analog Input section. 3 Specification is for device in free air: SOIC-10: JA = 200C/W.
ORDERING GUIDE
Model AD7686ARM-REEL7 EVAL-AD7686CB1 EVAL-CONTROL BRD2 2 EVAL-CONTROL BRD3 2 Temperature Range -40C to +85C Package Description SOIC-10 Evaluation Board Controller Board Controller Board Package Option RM-10
NOTES 1 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes. 2 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
AD7686 PIN CONFIGURATION
500A IOL
To SDO CL 50pF 500A IOH
+1.4V
REF 1 VDD 2
10 9
OVDD SDI SCK SDO CNV
Figure 1. Load Circuit for Digital Interface Timing.
IN+ 3 IN- 4 GND 5
AD7686
8 7 6
2V 0.8V
tDELAY
2V 0.8V
tDELAY
2V 0.8V
Figure 2. Voltage Reference Levels for Timing.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7686 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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PRELIMINARY TECHNICAL DATA AD7686
PIN FUNCTION DESCRIPTIONS
Pin #
1 2 3 4 5 6
Mnemonic
REF VDD IN+ INGND CNV AI P AI AI P DI
Function
Reference Input Voltage. The REF range is from TBD to VDD. It is referred to the GND ground. This pin should be decoupled closely to the pin with a TBD Fcapacitor. Input Power Supply. Analog Input. It is referred to IN-. The voltage difference between IN+ and IN- range is 0V to VREF. Sense Analog Input Ground. To be connected to the analog ground plane or to a remote sense ground. Power Supply Ground. Convert Input. This input has multiple functions. It initiates the conversions on its leading edge. The interface mode of the part, Chain or CS mode, is selected on its leading edge. In CS mode, it can enable the serial output signals when low. In Chain mode, the data should be read while CNV is high. Serial Data Output. The conversion result or the programming configuration word are ouput on this pin. It is synchronized to SCK. Serial Data Clock Input. Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: The Chain mode is selected if SDI is low on or just before the CNV rising edge. In this Chain mode, SDI could be used as a data input to daisy chain the conversion results from two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. The CS mode is selected if SDI is high on or just before the CNV rising edge. In this CS mode, either SDI or CNV can enable the serial output signals when low. Output Interface Digital Power. Nominally at the same supply than the host interface (2.5V, 3V or 5V).
7 8 9
SDO SCK SDI
DO DI DI
10
OVDD
P
NOTES AI = Analog Input DI = Digital Input DO = Digital Output P = Power
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PRELIMINARY TECHNICAL DATA AD7686
DEFINITION OF SPECIFICATIONS INTEGRAL NONLINEARITY ERROR (INL) EFFECTIVE NUMBER OF BITS (ENOB)
Linearity error refers to the deviation of each individual code from a line drawn from "negative full scale" through "positive full scale". The point used as "negative full scale" occurs 1/2 LSB before the first code transition. "Positive full scale" is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line.
DIFFERENTIAL NONLINEARITY ERROR (DNL)
ENOB is a measurement of the resolution with a sine wave input. It is related to S/(N+D) by the following formula: ENOB = (S/[N+D] dB - 1.76)/6.02) and is expressed in bits.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels.
SIGNAL-TO-NOISE RATIO (SNR)
In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed.
GAIN ERROR
SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels.
SIGNAL TO (NOISE + DISTORTION) RATIO (S/[N+D])
The last transition (from 111 . . . 10 to 111 . . . 11) should occur for an analog voltage 1 1/2 LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the actual level of the last transition from the ideal level after the offset has been adjusted out.
OFFSET ERROR
S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in decibels.
APERTURE DELAY
The first transition should occur at a level 1/2 LSB above analog ground (38.1 V for the 0 V to 5 V range). The offset error is the deviation of the actual transition from that point.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
Aperture delay is a measure of the acquisition performance and is measured from the falling edge of the CNV input to when the input signal is held for a conversion.
TRANSIENT RESPONSE
The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal.
The time required for the AD7686 to achieve its rated accuracy after a full-scale step function is applied to its input.
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PRELIMINARY TECHNICAL DATA AD7686
Modes of Operation The AD7686 features three modes of operations, Warp, Normal, and Impulse. The suitability of each mode is application dependant. Warp mode allows the fastest conversion rate up to 550 kSPS. However, in this mode, and this mode only, the full specified accuracy is guaranteed only when the time between conversion does not exceed 1 ms. If the time between two consecutive conversions is longer than 1 ms, for instance, after power-up, the first conversion result should be ignored. This mode makes the AD7686 ideal for applications where both high accuracy and fast sample rate are required. Normal mode is the fastest mode (450 kSPS) without any conversion rate limitations. This mode makes the AD7686 ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. Impulse mode is the lowest power dissipation mode, allowing power saving between conversions. The maximum throughput in this mode is 380 kSPS. When operating at 1 kSPS, for example, it typically consumes only 80 W. This feature makes the AD7686 ideal for battery-powered applications. on board conversion clock, the serial clock SCK is not required for the conversion process. After the conversion is complete, whatever the CNV state is, the part returns automatically in a power-down mode with the track and hold in track position.
CS MODE
The CS mode is selected if SDI is high on or just before the CNV rising edge. In CS mode, the data line SDO is in high impedance while both CNV and SDI are held high. In this mode, the data can be read by either bringing CNV low while SDI is held high, or bringing SDI low while CNV is held high. When CNV or SDI goes low, the MSB is output on SDO. The remaining data bits are then clocked by subsequent SCK falling edges. SDO is available on both SCK edges. After the 16th SCK falling edge or CNV goes high whichever is the earliest, the SDO returns to high impedance. Figure 3 shows a detailed timing diagram of this interface mode with a 3 wires connection (SDI tied to VDD). Figure 4 shows a detailed timing diagram of this interface mode with a 4 wires connection (SDI is used to select the data).
DIGITAL INTERFACE
In spite of its reduced number of pins, the AD7686 offers flexibility in its interface modes: The AD7686, used in "CS mode", is compatible to SPI, QSPI digital hosts and DSPs (e.g.: ADSP-219x). This interface can used either 3 or 4 wires. 3 wires interface using CNV, SCK and SDO signals, minimizes wiring connections useful , for instance, in isolated applications. 4 wires interface using SDI, CNV, SCK and SDO signals allows CNV, used to initiate the conversions, to be independant of the reading timing (SDI). That is useful in, low sampling jitter or simultaneous sampling applications or applications where other SPI devices like analog multiplexers are used. The AD7686, used in "Chain mode", provides a "daisy chain" feature using the SDI input for cascading multiple ADCs on a single data line. The AD7686 also offers the possibility, as an option and with both modes, to force a start bit in front of the 16 data bits. This start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. In any mode, the CNV rising edge is used as a sampling edge. It puts the track and hold in hold position and initiates the conversion process. Because the AD7686 has an
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PRELIMINARY TECHNICAL DATA AD7686
SDI = 1
t3
t4
CNV
t1
ACQUISITION CONVERSION
t2
ACQUISITION
t5
t7
15
SCK
1
2
14
16
t 10
SDO D15
t8
D14
t6
D13
D1 D0
t 11
t9
Figure 3. Serial Interface Timing ( CS mode : SDI High ).
t3
CNV
t 13
SDI
t 12
ACQUISITION CONVERSION
t2
ACQUISITION
t1
t5
t7
15 16
SCK
1
2
14
t 10
SDO D15
t8
D14 D13
t6
D1 D0
t 11
t9
Figure 4. Serial Interface Timing ( CS mode : SDI used as a CS signal ).
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PRELIMINARY TECHNICAL DATA AD7686
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
10-Lead SOIC (RM-10)
0.124 (3.15) 0.112 (2.84)
10
6
0.124 (3.15) 0.112 (2.84)
1 5
0.199 (5.05) 0.187 (4.75)
PIN 1 0.0197 (0.50) BSC
0.038 (0.97) 0.030 (0.76)
0.122 (3.10) 0.110 (2.79)
0.043 (1.09) 0.037 (0.94) 68 SEATING 0.006 (0.15) 0.016 (0.41) PLANE 08 0.011 (0.28) 0.002 (0.05) 0.006 (0.15) 0.003 (0.08)
0.120 (3.05) 0.112 (2.84)
0.022 (0.56) 0.021 (0.53)
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